• Make allows us to specify what depends on what and how to update things that are out of date.


  • Use # for comments in Makefiles.
  • Write rules as target: dependencies.
  • Specify update actions in a tab-indented block under the rule.
  • Use .PHONY to mark targets that don’t correspond to files.

Automatic Variables

  • Use $@ to refer to the target of the current rule.
  • Use $^ to refer to the dependencies of the current rule.
  • Use $< to refer to the first dependency of the current rule.

Dependencies on Data and Code

  • Make results depend on processing scripts as well as data files.
  • Dependencies are transitive: if A depends on B and B depends on C, a change to C will indirectly trigger an update to A.

Pattern Rules

  • Use the wildcard % as a placeholder in targets and dependencies.
  • Use the special variable $* to refer to matching sets of files in actions.


  • Define variables by assigning values to names.
  • Reference variables using $(...).


  • Make is actually a small programming language with many built-in functions.
  • Use wildcard function to get lists of files matching a pattern.
  • Use patsubst function to rewrite file names.

Self-Documenting Makefiles

  • Document Makefiles by adding specially-formatted comments and a target to extract and format them.


  • Makefiles save time by automating repetitive work, and save thinking by documenting how to reproduce results.